To provide more dense memory for computing operations, concepts involving memory devices (which may be referred to as 3D stacked memory, or stacked memory) having a plurality of closely coupled memory elements have been developed. A 3D stacked memory may include coupled layers or packages of DRAM (dynamic random-access memory) memory elements, which may be referred to as the strata of a memory stack. Stacked memory may be utilized to provide a great amount of computer memory in a single device or package, where the device or package may also include certain system components, such as a memory controller and CPU (central processing unit).
The development of stacked memory and other similar memory architecture requires testing of such devices, where the testing may include testing of memory and testing of I/O (input/output) links.
However, the structure of stacked memory devices provides challenges to effective testing. In particular, the stacked memory device architecture contains micro-bump connections that cannot be accessed for testing of the memory interface, and thus conventional testing is not usable for such devices.